The present invention relates to a buffering circuit of a semiconductor memory device, and more specifically to a buffering circuit including a plurality of buffers divided into some groups, of which each group is activated independent of the other.
In general a number of buffers are employed for converting external signal of TTL (transistor-transistor-logic) level into internal signals of CMOS (complementary metal-oxide-semiconductor) level in a semiconductor memory device. The buffers are disposed at the terminal pads to receive the external signals such as address signals, data signals, and command/control signals.
FIG. 1 shows a construction of the conventional buffering circuit in a semiconductor memory device, in which command buffers and address buffers are simultaneously disabled during a refresh operation for the purpose of reduce current consumption.
Referring to FIG. 1, the buffering circuit includes refresh signal generator 10, buffer controller 20, command buffers group 30, and address buffers group 40.
The refresh signal generator 10 generates refresh signal REF by receiving self-refresh signal SREF and auto-refresh signal AREF and performing a logic operation of these signals through NOR gate NOR1, and inverter IV2. The buffer controller 20 receives clock enable signal CKE from clock enable latch 21, and then generates buffer enable signal E1 through inverter IV1, NOR gate NOR2, and inverter IV3. The inverter IV1 applies an output signal of the latch 21 into the NOR gate NOR2 which also receives the refresh signal REF. An output signal from the NOR gate NOR2 is converted into the buffer enable signal E1 through the inverter IV3. The command buffers group 30 includes chip selection signal buffer CSBUF (hereinafter, referred to as CS buffer), row address strobe signal buffer RASBUF (hereafter, RAS buffer), column address strobe signal buffer CASBUF (hereinafter, CAS buffer), and write enable signal buffer WEBUF (hereinafter, WE buffer). The buffers CSBUF, RASBUF, CASBUF, and WEBUF are activated in response to signal E1a that is logically reversed one of the buffer enable signal E1 through inverter IV4. The address buffers group 40 includes a plurality of address buffers A1xcx9cAn that are enabled in response to signal E1b that is logically reversed one of the buffer enable signal E1 through inverter IV5. The E1a and E1b will be referred to as the first and second reverse signals, respectively, of the buffer enable signal E1.
The RAS buffer, the CAS buffer, and the WE buffer within the group 30 have the same circuit architecture, except for their corresponding input signals. Hence, the circuit shown in FIG. 2 can correspond to any one of the WEBUF, RASBUF, and CASBUF. Therefore, according to a kine d of buffer input signal VINZ1 can be replaced with one of the write enable signal, the row address strobe signal, or the column address strobe signal. Also, output signal VOUTZ1 can be replaced with one of the write enable signal, the row address strobe signal, or the column address strobe signal. The buffer of FIG. 2 is formed of well-known differential amplifier DA1 which becomes active in response to the first reverse signal E1a and compares the input signal VINZ1 with reference to voltage VREF, and delay circuit DL1, which converts an output signal into an output signal VOUTZ1 after reverse/delay of the output signal of the amplifier DA1.
The address buffers A1xcx9cAn within the group 40 are constructed in the same constructions with that shown in FIG. 2, exept that the differential amplifier is enabled by the second reverse signal E1b. 
FIG. 3 shows a detailed circuit architecture of the CS buffer in the command buffer group 30, including differential amplifier DA2, delay circuits DL2 and DL3, NOR gate NOR3, and inverter IV6. The differential amplifier DA2, is enabled by the first reverse signal E1a, and generates an output signal of comparing input signal VINZ2 (i.e., an external CS signal) with the reference to voltage VREF. The delay circuit DL3 converts the output signal of the differential amplifier DA2 into the first delay signal A, and the delay circuit DL2 converts the buffer enable signal E1 into the second delay signal B. The first and second delay signals A and B are applied to the NOR gate NOR3. An output signal of the NOR gate NOR3 turns into output signal VOUTZ2 (i.e., the chip selection signal) through the inverter IV6.
Referring to FIG. 4, which describes an operation of the buffering circuit shown in FIG. 1, if there is either of the self-refresh signal SREF or the auto-refresh signal AREF which goes up to a high level, the buffer enable signal E1 is set on a high level regardless of the state of the clock enable signal CKE.
In this case, the first and second reverse signals, E1a and E1b, are low levels, causing the differential amplifiers DA1 and DA2 to be disable, and thereby the output signals from the differential amplifiers DA1 and DA2 turn into high levels. Accordingly, the output signal of the differential amplifier DA1 that is assigned to the CAS buffer CASBUF, the RAS buffer RASBUF, or the WE buffer WEBUF is established at a low level after passing through the delay circuit DL1.
Meanwhile, in the CS buffer CSBUF, as the first and second delay signals A and B are applied to the NOR gate NOR3 with low and high levels, respectively, the output signal VOUTZ2 goes up to a high level.
At the time of terminating the refresh mode, t1 in FIG. 4, the buffer enable signal E1 turne to a low level. In the CS buffer CSBUF, the differential amplifier DA2 is enabled in response to the first reverse signal of high level, and then outputs an amplified signal of the input signal VINZ2. The delay signal DL3 inverts and delays the output signal of the differential amplifier DA2, and then makes the first delay signal A.
The first delay signal A is applied to the NOR gate NOR3 together with the second delay signal B that goes to a low level after the delay time. As shown in FIG. 4, after the refresh mode is terminated at the time t1, the second delay signal B falls down to a low level before the CS buffer CSBUF receives the input signal VINZ2. As a result, around t2 after the second delay signal B has been changed to a low level, there is a period that the output signal VOUTZ2 has a short pulse of a low level when the input signal VINZ2 is applied thereto with a low level that makes the first delay signal turne into a high level.
In conttary, at the time t1 finishing the refresh mode, the first reverse signal E1a of a high level enables the RAS buffer RASBUF, the CAS buffer CASBUF, and the WE buffer WEBUF to be conductive. As the output signal VOUTZ1 is still held on a low level because the input signal VINZ1 has not been transferred through the differential amplifier DA1 and the delay circuit DL1 even after the activation of the buffer, it may occur to put the semiconductor memory device into a state of a mode register set (MRS) when the output signal VOUTZ2 figures out at the low pulse as shown in FIG. 4.
Such an abnormal entrance into the MRS mode is not intended to be designed and thereby may cause a malfunction responding to undesirable external signals.
While the undesirable entrance into the MRS is prevented in the self-refresh mode by controlling an enable timing of an internal buffer where the output signal VOUTZ is buffered therethrough to be utilized as an internal command signal in the memory device, the auto-refresh mode can not be free from the malfunction at the time of terminating as aforementioned.
Although there has been various ways to overcome the improper timing with the second delay circuit DL2, it has limits due to large fluctuation of erroneous rates involved in operational factors such as delay timings that are physically affected by supply voltages, temperature, and variations in manufacturing process, rather it reduces operating speed in the environment of high frequency data processing.
Otherwise, additional control logic circuits to regulate the malfunction would make the circuit composition complicate and increase a topological size of the memory chip.
It is, therefore, an object of the present invention to provide a buffering circuit capable of securing reliable generation of buffered output signals.
It is another object of the invention to provide a buffering circuit preventing a undesirable entrance into a mode register set mode after a refresh operation.
It is still another object of the invention to provide a buffering circuit which controls activation operation of input buffers properly.
In order to attain the above objects, a buffering circuit according to the present invention has a plurality of signal input buffers being divided into a multiplicity of groups. The buffers of each group are controlled by an independent enable signal.
Furthermore, with distinguishing operation modes into a refresh mode and non-refresh mode, as well as the refresh mode into a self-refresh and a auto-refresh, the buffers of each group are independently conductive in accordance with a state of mode.
A buffer controller uses the first refresh signal for discriminating between the refresh mode and the non-refresh mode, and the second refresh signal for designating an alternative one of various refresh modes, and then generates enable signals for the signal input buffers segmented into the multiplicity of groups.
The buffer controller includes the first controller for generating the first control signal to discriminate the refresh mode from and non-refresh mode and to control the signal input buffers, and the second controller for generating the second control signal to operate the signal input buffers.
The signal input buffers of an input buffer group are for example divided into two operable groups by the first and second control signals, respectively.